3D-ROM - A First Practical Step Towards 3D-IC

		At a Glance
	A new read-only memory technology is proposed that can be embedded inexpensively on any IC without consuming any silicon real estate. Three-dimensional Read-Only Memory (3D-ROM) technology uses well understood metal and amorphous silicon deposition technologies to add memory over the existing interconnect structure on an IC. A layer containing 120 MB/cm2 of ROM can be added with about 5 masking steps.

G. Zhang, Ph. D.

The three-dimensional IC (3D-IC)^1,2 is considered the ultimate IC structure of the future. In a 3D-IC, stacked active IC layers are sandwiched between insulating layers. It promises high packing density, high speed, parallel signal processing, and integration of many functions on a single "chip."¹ A broad range of applications are expected for this technology.

3D-IC has been extensively researched during last decade. Although great strides have been made towards its success, 3D-IC still faces several technical challenges, especially in the areas of recrystalliztion of silicon films and thermal budget issues.

To reduce statistical variations in transistor drive current and leakage current, the channel region of each transistor should be within a single silicon grain. Techniques such as germanium-seeded lateral crystallization have demonstrated the capability to control the grain location for a standalone TFT.³However, in an active VLSI layer where TFT's are closely spaced, the effectiveness of these techniques still needs to be demonstrated.

Fig. 1 A perspective and Cross-sectional view of a 3D-ROM.

The fabrication of deep sub-micron TFT inherently involves several high temperature steps, the most critical one being the growth of gate oxide. To grow a high quality thin gate oxide in the deep sub-micron technology, wafers are processed at a temperature as high as 850°C. This high-temperature step certainly poses a threat to the integrity of the metallization in the lower IC layers.

Although it may take time before 3D-ICs utilizing active devices become commercially viable, read only memory based on passive devices can be added on top of active device ICs using well understood methods. This three-dimensional read-only memory (3D-ROM)⁴ uses metal-to-metal diodes as the memory cell. While avoiding most of the technical hurdles faced by 3D-IC, 3D-ROM possesses many of its merits.

3D-ROM structure

In the basic 3D-ROM structure, multiple levels of read-only memory can be stacked on top of each other, with an interlevel dielectric separating the ROM levels (Fig. 1). These ROM levels can be placed on top of any conventional IC structure, such as microprocessor, flash or EEPROM. The only addition required on the chip is the decoder for the 3D-ROM.

Each ROM level consists of a set of word lines in one metal layer and a set of bit lines in another metal layer, separated by an insulating layer (Fig. 2). The cross points between word and bit lines contain the individual ROM cells.

Fig. 2 A circuit schematic of ROM array in one 3D-ROM memory level.

To avoid the technical hurdles faced by 3D-ICs, 3D-ROM uses passive devices, such as metal-to-metal diodes, to make memory cells (Fig. 2). The digital information ("0" or "1") stored in a ROM cell is distinguished by the existence or absence of a diode between the word line and the bit line at the ROM cell. Here, diodes are used to minimize cross-talk between bit lines. With a diode, the memory cell represents a logic "1"; if no diode can be sensed, a logic "0" is stored in this memory cell. During read operation, a read voltage is applied on the word line. If there is a diode, the bit line will sense a read current. Otherwise, no read current can be sensed. Readout circuitry then converts read current to different output voltage level according to its magnitude. As a result, the logic state of the ROM cell can be detected.

The structure of metal-to-metal diode is similar to metal-to-metal antifuse. A p-n junction made of amorphous silicon (a-Si) is sandwiched between the word and bit lines to form the diode. Other semiconductor materials such as SiC may also be used. Preferably, there will be a barrier layer between the diode layer and electrodes, such as tungsten or titanium nitride.

Since it is based on amorphous materials, 3D-ROM does not require recrystallization. Amorphous silicon technology is a mature technology. Flat panel display (FPD) industry has been using a-Si in thin-film transistors (TFT) for years.⁵ Moreover, a-Si can be deposited and doped at a temperatures below 300°C. Since processing in this temperature range will not affect the IC structure at the substrate level, the 3D-ROM manufacturing process is compatible with standard IC processes.

Fig. 3 A 3D-MPROM represents digital information through the existence of a via.

A 3D-ROM can be factory-programmed or user-programmable. One example of factory-programming is mask-programmed 3D-ROM (3D-MPROM) (Fig. 3).⁶ In a 3D-MPROM, the existence or absence of a diode is controlled by the mask set used. For a logic "0" cell, an insulating layer, such as a field oxide, separates the word line from the bit line, so that no diode can be sensed (Fig. 3a). For a logic "1" cell, the diode is formed between the word and bit lines (Fig. 3b).

User-programmable ROM provides flexibility to end users. One example is electrically-programmable 3D-ROM (3D-EPROM).⁷ In a 3D-EPROM (Fig. 4), the logic state of a ROM cell is determined by the integrity of an antifuse layer. The antifuse layer is typically comprised of intrinsic a-Si (~1000?thick) or metal oxide (a few hundred ?thick). Prior to programming, the antifuse layer is intact and exhibits a high resistance.

Fig. 4 A 3D-EPROM cell uses antifuse to represent digital information.

Thus, no diode can sensed between the word and bit lines. The memory cell therefore represents logic "0". Upon application of a programming pulse, the antifuse layer goes through electrical breakdown, and reacts with surrounding metallic materials to form conductive filaments. A ROM cell with a programmed antifuse layer represents logic "1." Although typical antifuse technology is write-once, chalcogenide glass and other materials have been studied as candidates for multiple-write antifuse.⁸

Fig. 5 A layout of 3D-MPROM corresponding to the circuit diagram in Fig. 2. The cell with a via is a logic "1", otherwise "0".

A layout of 3D-ROM is illustrated in Fig. 5. Here, 3D-MPROM is used as an example. A number of word lines run in parallel along the x axis. Bit lines are perpendicular to word lines and run along the y axis. There is a ROM cell at each intersection. It represents logic "1" if there is a via, otherwise "0". The minimum line spacing between the word (bit) lines is determined by the minimum contacted interconnect pitch P (P'2F, where F is the minimum feature size). Each ROM cell occupies an area of A = P² ' 4F². At the 180 nm node, P is 460 nm and this results in a cell area of 0.21µm². A memory density up to 60MB/cm²/level can be achieved. Using flash or EEPROM technology as a baseline, the memory density at each ROM level can be twice as much (Table 1).

Table 1. Proposed Spec. of 3D-ROM vs. Conventional Storage Devices targeted for embedded systems and information appliances.

According to SIA's National Technology Roadmap, six to seven metal levels will be common for IC products at the 180 nm node,⁹ and each 3D-ROM level needs only two metal levels. Conventional memory ICs need only three metal levels, so two ROM levels could be incorporated. Logic ICs typically use more metal levels, but it is feasible to build at least one ROM level above it.

Since each ROM level is equivalent to two metallization levels with an additional a-Si p-n diode in-between, the total number of masking steps to make each ROM level is about five. In contrast, 20-30 masking steps are required for flash or EEPROM, so the manufacturing cost of one ROM level is at least 5?lower than that of a flash or EEPROM. Combined with the fact that memory density at each ROM level can be at least twice as much as for flash or EEPROM, the wafer cost per bit for 3D-ROM can be less than one-tenth of that of flash, EEPROM or other conventional transistor-based memory. Also, since it is embedded, 3D-ROM does not incur extra packaging cost. 3D-ROM has the potential to be an extremely low cost memory technology (Table 1).

SoC and its impact on computer architecture

A typical system-on-a-chip (SoC) is composed of a microprocessor, embedded RAM (SRAM, DRAM) and embedded NVM (non-volatile memory: flash, ROM). 3D-ROM is well suited to be the NVM component for an SoC. Since integration of the 3D-ROM is done vertically, except for a small fraction of substrate area needed by its decoder, 3D-ROM does not compete against other embedded memory for silicon real estate.

Fig. 6 3D-ROM interfaces with the IC at the substrate level through tens of thousands of interconnecting vias.

A significant speed advantage that 3D-ROM offers is the ability to use very wide buses. The number of interconnecting vias through which the 3D-ROM interfaces with the IC at the substrate level can be on the order of tens of thousands (Fig. 6). The realization of massive parallel data transfer can results in a very high data rate (>0.5 GB/s) (Table 1).

Although both 3D-ROM and hard-disk drive (HDD) are targeted for information storage, 3D-ROM has a much smaller latency and larger bandwidth (Table 1). These attributes can have a significant impact on computer architecture. To date, the memory hierarchy of a conventional computer system includes one or two levels of cache (SRAM), main memory (DRAM) and secondary memory (HDD). Because its latency is ~10 ms and its bandwidth is ~5-50 MB/s, HDD has a large access time (700,000-6,000,000 clock cycles).¹⁰ This large access time is also the miss penalty to the main memory. To limit the memory stall to ~1 clock cycle, the main memory miss rate has to be limited to 0.001 - 0.00001% To satisfy such a stringent requirement on miss rate, a large amount of DRAM is needed (16-8192 MB).10

In a 3D-ROM computer system, the 3D-ROM is used as the permanent storage device for software. Because it takes only 100-3,000 clock cycles to fetch data from the 3D-ROM, the memory level preceding the 3D-ROM in the memory hierarchy can accept a miss rate as high as 0.1%-1%. Thus, the amount of DRAM required in a 3D-ROM computer system can be significantly reduced. In fact, a miss rate of 0.1%-1% can be handled by the second level cache, or, just the on-chip cache in a low-end system.

Because only semiconductor memories are involved in a 3D-ROM computer system and much less main memory is required, concepts such as "computer-on-a-chip" (ConC) or "computer-in-a-package" (CinP) can be realized. For example, 3D-ROM can be integrated with IRAM (intelligent-RAM)¹¹ to materialize a ConC, or, 3D-ROM can be integrated on top of a second-level cache (or, a DRAM) and placed in the same package with a microprocessor - a realization of CinP.

In a ConC or aCinP, software is embedded in the IC chip. 3D-MPROM is a simple technology for storing that embedded software. It is particularly suitable for system software, which is fixed and requires a large memory space. It can be integrated with 3D-EPROM, flash, EEPROM and other writable NVM on the same chip to help address the need for software upgrades. With most of the information stored in 3D-ROM, the requirement on the flash and EEPROM capacity can be eased. This memory architecture allows low-cost, large-capacity storage in the 3D-ROM while maintaining the flexibility and field-upgradibility of the flash and EEPROM.

It is particularly suitable for object-oriented software. For example, Java has a large library that contains most of its functionality. Also, Java progresses and extends its facilities by the addition of libraries. While the Java library demands large memory space, Java programs are generally compact and can be frequently updated from the internet. To embed Java into a ConC/CinP, the original release of the library can be hard-coded in the 3D-MPROM. In the case of a new Java release, library addition can be stored in 3D-EPROM, flash or EEPROM. Java programs can be stored in flash or EEPROM. Combining 3D-ROM with flash or EEPROM, embedded software can stay current and a ConC/CinP can have an extended field lifetime.

Summary

3D-ROM utilizes metal-to-metal diodes as its memory elements. It does not use exotic materials and the thermal budget for manufacturing it is small. It is compatible with standard IC process, and it can be readily integrated with a conventional IC in a vertical fashion. With the help of 3D-ROM, concepts such as computer on a chip (CoC) and computer in a package (CinP) can be realized. 3D-ROM can enable SoC products that otherwise would not have been economically feasible.

The author would like to thank many friends for valuable discussions.

G. Zhang, Ph. D.

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